Dynamic and partial reconfiguration of Zynq 7000 under Linux

Muhammed Soubhi Al Kadi, Patrick Rudolph, Diana Göhringer, Michael Hübner

2013 International Conference on Reconfigurable Computing and FPFA, December 9-11, 2013, Cancun Mexico


Dynamic and partial reconfiguration is a well-known technique to update the configuration of a field programmable gate array (FPGA) at runtime. Xilinx FPGAs support this feature which enables extensive research in this domain. However, until today the usage and exploitation of partial reconfiguration has a hurdle. The complex development process, as well as the required control at runtime keeps this technique away from many applications where it would be beneficial and lead to a reduction of costs and power consumption since a smaller FPGA can host more hardware modules due to a temporal partition and configuration in a time sequence. This paper shows an approach using the novel Zynq FPGA architecture from Xilinx. The partial reconfiguration is usable with a Linux realized on the dual core ARM 9 processor. A reconfigurable area provides space for accelerators which can be loaded and updated at runtime

tags: FPGA, reconfiguration, Zync7000