The Cadence Academic Network was launched in 2007 by Cadence Europe. The aim is to promote the proliferation of leading-edge technologies and methodologies at universities renowned for their engineering and design excellence. A knowledge network among selected European universities, research institutes, industry advisors and Cadence was established to facilitate the sharing of technology expertise in the areas of verification, design and implementation of microelectronic systems. The Cadence Academic Network, therefore, significantly support and improve the universities activities.

The Chair for Embedded Systems of Information Technology (ESIT) is a lead institution of the Cadence Academic Network and focuses on the development of Embedded Systems with novel reconfigurable hardware technologies and specific and adaptive processor architectures. The main research topics include:

  • Development of application specific and adaptive processor architectures including development tools
  • Development of reconfigurable hardware architectures (field programmable gate arrays) as well as development tools
  • Virtualization techniques for the development and verification of complex system architectures
  • Run-time virtualization of heterogeneous hardware architectures
  • Ultra low power high performance embedded computing

Find out more about current research projects


Prof. Dr.-Ing. Micha­el Hüb­ner

Te­le­fon: (+49)(0)234 / 32 - 25975
Fax: (+49)(0)234 / 32 - 14499

Courses where Cadence technology is being used:

The Cadence Academic Network is providing its technical information via the LinkedIn network. The groups are moderated by the lead institutions of the academic network, ensuring a constant flow of reviewed information relevant to academia. For an overview of the LinkedIn groups’ structure, as well as guidelines on how to subscribe to the groups of your interest, visit the Cadence Academic Network at LinkedIn webpage.

The subgroup "IP Design, Integration and Validation" can be found here .

Ca­dence is a re­gis­te­red trade­mark of Ca­dence De­sign Sys­tems, Inc., 2655 Seely Ave­nue, San Jose, CA 95134.